`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   22:19:26 12/05/2012
// Design Name:   TRIG_DECIDE_UNIT
// Module Name:   D:/Workspace/xilinx workspace/HFM_DETECTOR/trig_decide_simu.v
// Project Name:  HFM_DETECTOR
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: TRIG_DECIDE_UNIT
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module trig_decide_simu;

	// Inputs
	reg clk;
	reg rst;
	reg strength_detect;
	reg [32:0] coef_numerator;
	reg [31:0] coef_denominator;

	// Outputs
	wire trig;

	// Instantiate the Unit Under Test (UUT)
	TRIG_DECIDE_UNIT uut (
		.clk(clk), 
		.rst(rst), 
		.strength_detect(strength_detect), 
		.coef_numerator(coef_numerator), 
		.coef_denominator(coef_denominator), 
		.trig(trig)
	);

	integer i;
	always #10 clk = ~clk;

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		strength_detect = 0;
		coef_numerator = 0;
		coef_denominator = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
        
		rst = 1;
		
		strength_detect = 1;
        
		// Add stimulus here
		for(i=0;i<50;i=i+1)
			#20 
			begin
			coef_numerator = i+12;
			coef_denominator = 2*i;
			end
			
		#100
		
		strength_detect = 0;

		for(i=0;i<50;i=i+1)
			#20 
			begin
			coef_numerator = i+12;
			coef_denominator = 2*i;
			end

	end
      
endmodule

